The input current, IPD, flows in the collector of an optimally scaled NPN transistor, connected in a feedback path around a low offset JFET amplifier. The current summing input node operates at a constant voltage, independent of current, with a default value of 0.5 V; this may be adjusted over a wide range. An adaptive biasing scheme is provided for reducing photo-diode dark current at very low light input levels. The VPDB pin applies approximately 0.1 V reverse bias across the photodiode for IPD = 100 pA, rising linearly to 2.0 V of reverse bias at IPD = 10 mA to improve response time at higher power levels. The input pin INPT is flanked by the VSUM guard pins that track the voltage at the summing node. Connecting the exposed pad of the device to the VSUM pins provides a continuous guard to minimize leakage into the INPT pin.
The default value of the logarithmic slope at the VLOG output is set by an internal 5 k? resistor. Logarithmic slope can be lowered with an external shunt resistor or increased using the buffer and a pair of external feedback resistors. The addition of a capacitor at the VLOG pin provides a simple low-pass filter. The intermediate voltage, VLOG, is buffered in an output stage that can swing to within about 100 mV of ground and the posi- tive supply, VPS, and provides a peak current drive capacity of ±20 mA. An on-board 2 V reference is provided to facilitate the repositioning of the intercept. The incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. At IPD =1 nA, the bandwidth of the ADL5303 is approximately 2 kHz increasing in proportion to IPD up to a maximum value of 10 MHz.
