The part is well suited for half- and full-duplex applications. The digital interface is extremely flexible, allowing simple interfacing to digital back ends that support half- or full-duplex data transfers, often allowing the AD9869 to replace discrete ADC and DAC solutions. Power-saving modes include the ability to reduce power consumption of individual functional blocks or power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks, from a single crystal or clock source.
The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and 12-bit ADC. The low noise RxPGA has a programmable gain range of -12dB to +48dB in 1dB steps. Its input referred noise is less than 3nV for gain settings beyond 36dB. The receive path LPF cutoff frequency can be set over a 15 to 35MHz range or it can be simply bypassed. The 12-bit ADC achieves excellent dynamic performance up to an 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.
AD9869 provides a highly integrated solution for many broadband modems. It is available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature range (-40°C to +85°C).
